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Modeling instruction semantics in ADL processor descriptions for C compiler retargeting. (English) Zbl 1103.68453

Summary: Today’s application specific instruction-set processor design methodology often employs centralized architecture description language processor models, from which software tools, such as C compiler, assembler, linker, and instruction-set simulator, can be automatically generated. Among these tools, the C compiler is becoming more and more important. However, the generation of C compilers requires high-level architecture information rather than low-level details needed by simulator generation. This makes it particularly difficult to include different aspects of the target architectureinto one single model, and meanwhile keeping consistency.
This paper presents a modeling style, which is able to capture high- and low-level architectural information at the same time and make it possible to drive both the C compiler and the simulator generation without sacrificing the modeling flexibility. The proposed approach has been successfully applied to model a number of contemporary, real-world processor architectures.

MSC:

68N20 Theory of compilers and interpreters
68M99 Computer system organization

Software:

ISDL; MIMOLA
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References:

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