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Transactional mutex locks. (English) Zbl 1395.68086

D’Ambra, Pasqua (ed.) et al., Euro-Par 2010 – parallel processing. 16th international Euro-Par conference, Ischia, Italy, August 31 – September 3, 2010. Proceedings, Part II. Berlin: Springer (ISBN 978-3-642-15290-0/pbk). Lecture Notes in Computer Science 6272, 2-13 (2010).
Summary: Mutual exclusion (mutex) locks limit concurrency but offer low single-thread latency. Software transactional memory (STM) typically has much higher latency, but scales well. We present transactional mutex locks (TML), which attempt to achieve the best of both worlds for read-dominated workloads. We also propose compiler optimizations that reduce the latency of TML to within a small fraction of mutex overheads.
Our evaluation of TML, using microbenchmarks on the x86 and SPARC architectures, is promising. Using optimized spinlocks and the TL2 STM algorithm as baselines, we find that TML provides the low latency of locks at low thread levels, and the scalability of STM for read-dominated workloads. These results suggest that TML is a good reference implementation to use when evaluating STM algorithms, and that TML is a viable alternative to mutex locks for a variety of workloads.
For the entire collection see [Zbl 1198.68025].

MSC:

68N19 Other programming paradigms (object-oriented, sequential, concurrent, automatic, etc.)
68N20 Theory of compilers and interpreters

Software:

NOrec; RingSTM
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