Andreopoulos, Y.; Schelkens, P.; Lafruit, G.; Masselos, K.; Cornelis, J. High-level cache modeling for 2-D discrete wavelet transform implementations. (English) Zbl 1039.68046 J. VLSI Signal Process. Syst. Signal Image Video Technol. 34, No. 3, 209-226 (2003). Summary: The main implementations of the 2-D binary-tree discrete wavelet decomposition are theoretically analyzed and compared with respect to data-cache performance on instruction-set processor-based realizations. These implementations include various image-scanning techniques, from the classical row-column approach to the block-based and line-based methods, which are proposed in the framework of multimedia-coding standards. Analytical parameterized equations for the prediction of data-cache misses under general realistic assumptions are proposed. The accuracy and the consistency of the theory are verified through simulations on test platforms and a comparison is made with the results from a real platform. MSC: 68P30 Coding and information theory (compaction, compression, models of communication, encoding schemes, etc.) (aspects in computer science) Keywords:cache memories; discrete wavelet transform implementations; theoretical modeling PDF BibTeX XML Cite \textit{Y. Andreopoulos} et al., J. VLSI Signal Process. Syst. Signal Image Video Technol. 34, No. 3, 209--226 (2003; Zbl 1039.68046) Full Text: DOI