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SoftTOTEM: An FPGA implementation of the TOTEM parallel processor. (English) Zbl 1020.68802

Glesner, Manfred (ed.) et al., Field-programmable logic and applications. Reconfigurable computing is going mainstream. 12th international conference, FPL 2002, Montpellier, France, September 2-4, 2002. Proceedings. Berlin: Springer. Lect. Notes Comput. Sci. 2438, 1084-1087 (2002).
Summary: TOTEM is digital VLSI parallel processor ideally suitable for vector-matrix multiplication. As such, it provides the core computational engine for digital signal processing and artificial neural network algorithms. It has been implemented in the past as a full-custom IP core, achieving high data throughput at clock frequencies of up to 30 MHz. This paper presents the ’soft’ implementation of the TOTEM neural chip, and compares its cost and performance to previous ’hard’ implementations.
For the entire collection see [Zbl 1010.68847].

MSC:

68U99 Computing methodologies and applications
94C10 Switching theory, application of Boolean algebra; Boolean functions (MSC2010)

Software:

SoftTOTEM
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