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Design and verification of fault-tolerant components. (English) Zbl 1234.68040
Butler, Michael (ed.) et al., Methods, models and tools for fault tolerance. Berlin: Springer (ISBN 978-3-642-00866-5/pbk). Lecture Notes in Computer Science 5454, 57-84 (2009).
Summary: We present a systematic approach to design and verification of fault-tolerant components with real-time properties as found in embedded systems. A state machine model of the correct component is augmented with internal transitions that represent hypothesized faults. Also, constraints on the occurrence or timing of faults are included in this model. This model of a faulty component is then extended with fault detection and recovery mechanisms, again in the form of state machines. Desired properties of the component are model checked for each of the successive models. The models can be made relatively detailed such that they can serve directly as blueprints for engineering, and yet be amenable to exhaustive verification. The approach is illustrated with a design of a triple modular fault-tolerant system that is a real case we received from our collaborators in the aerospace field. We use UPPAAL to model and check this design. Model checking uses concrete parameters, so we extend the result with parametric analysis using abstractions of the automata in a rigorous verification.
For the entire collection see [Zbl 1160.68001].

MSC:
68M15 Reliability, testing and fault tolerance of networks and computer systems
68Q60 Specification and verification (program logics, model checking, etc.)
Software:
Uppaal; Uppaal2k
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References:
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