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On interprocess communication. II: Algorithms. (English) Zbl 0598.68023

Summary: Interprocess communication is studied without assuming any lower-level communication primitives. Three classes of communication registers are considered, and several constructions are given for implementing one class of register with a weaker class. The formalism developed in Part I [ibid. 1, 77–85 (1986; Zbl 0598.68022)] is used in proving the correctness of these constructions.

MSC:

68N25 Theory of operating systems
68Q85 Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.)
68W15 Distributed algorithms

Citations:

Zbl 0598.68022
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References:

[1] Courtois PJ, Heymans F, Parnas DL (1971) Concurrent control with ”readers” and ”writers”. Commun ACM 14:190–199
[2] Lamport L (1977) Concurrent reading and writing. Commun ACM 20:806–811 · Zbl 0361.68091
[3] Lamport L (1986) On interprocess communication. Part I: Basic formalism. Distributed Computing 1:77–85 · Zbl 0598.68022
[4] Lamport L (1985) Interprocess Communication. SRI Tech Rep
[5] Misra J (1986) Axioms for memory access in asynchronous hardware systems. ACM Trans Program Lang Syst 8:142–153 · Zbl 0593.68017
[6] Peterson GL (1983) Concurrent reading while writing. ACM Trans Program Lang Syst 5:46–55 · Zbl 0498.68010
This reference list is based on information provided by the publisher or from digital mathematics libraries. Its items are heuristically matched to zbMATH identifiers and may contain data conversion errors. It attempts to reflect the references listed in the original paper as accurately as possible without claiming the completeness or perfect precision of the matching.