Compact hardware implementations of the block ciphers mCRYPTON, NOEKEON, and SEA. (English) Zbl 1295.94132

Plos, Thomas; Dobraunig, Christoph; Hofinger, Markus; Oprisnik, Alexander; Wiesmeier, Christoph; Wiesmeier, Johannes

Galbraith, Steven (ed.) et al., Progress in cryptology – INDOCRYPT 2012. 13th international conference on cryptology in India, Kolkata, India, December 9–12, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-34930-0/pbk). Lecture Notes in Computer Science 7668, 358-377 (2012).

Summary: Compact hardware implementations are important for enabling security services on constrained devices like radio-frequency identification (RFID) tags or sensor nodes where chip area is highly limited. In this work we present compact hardware implementations of the block ciphers: mCrypton, NOEKEON, and SEA. Our implementations are significantly smaller in terms of chip area than the results available in related work. In case of NOEKEON, we even provide the first hardware-implementation results of this algorithm at all. Our implementations are designed as stand-alone hardware modules, contain an 8-bit interface for communication, and support encryption as well as decryption operation. We give results for different datapath widths and evaluate also the impact of using shift registers or latch-based memory instead of flip flops. The most-compact implementation of mCrypton requires 2 709 GEs when using a 130 nm CMOS process technology from Faraday. NOEKEON and SEA consume 2 880 and 2 562 GEs, respectively.
For the entire collection see [Zbl 1278.94004].

MSC:

94A60	Cryptography
68P25	Data encryption (aspects in computer science)

Keywords:

low-resource hardware implementation; RFID; symmetric cryptography; block cipher; low power consumption; shift register; 8-bit interface

Software:

mCrypton; NOEKEON