A characterization of ternary simulation of gate networks. (English) Zbl 0641.94030

Brzozowski, Janusz A.; Seger, Carl-Johan

IEEE Trans. Comput. 36, 1318-1327 (1987).

Ternary simulation techniques provide efficient methods for the analysis of the behavior of VLSI circuits. However, the results of ternary simulation have not been completely characterized. In this paper we prove a somewhat modified version of the Brzozowski-Yoeli conjecture (stated in 1976) that the results of the ternary simulation of a gate network N correspond to the results of the binary race analysis of \(\tilde N\) in the “multiple-winner” model, where \(\tilde N\) is the network N in which a delay has been inserted in each wire.

MSC:

94C10

Switching theory, application of Boolean algebra; Boolean functions (MSC2010)

Keywords:

asynchronous behavior; race detection; sequential networks; behavior of VLSI circuits; ternary simulation; Brzozowski-Yoeli conjecture; gate network