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Next-preserving branching bisimulation. (English) Zbl 1328.68141
Summary: Bisimulations are equivalence relations between transition systems which assure that certain aspects of the behaviour of the systems are the same in a related pair. For many applications it is not possible to maintain such an equivalence unless non-observable (stuttering) behaviour is ignored. However, existing bisimulation relations which permit the removal of non-observable behaviour are unable to preserve temporal logic formulas referring to the next step operator. In this paper we propose a family of next-preserving branching bisimulations to overcome this limitation.
Next-preserving branching bisimulations are parameterised with a natural number, indicating the nesting depth of the \(\mathbf X\) operators that the bisimulation preserves, while still allowing non-observable behaviour to be reduced. Based on R. J. van Glabbeek and W. P. Weijland’s notion of branching bisimulation with explicit divergence [J. ACM 43, No. 3, 555–600 (1996; Zbl 0882.68085)], we define the novel parameterised relation for which we prove the preservation of \(\mathrm{CTL}^\ast\) formulas with an \(\mathbf X\) operator-nesting depth that is not greater than the specified parameter. It can be shown that the family of next-preserving bisimulations constitutes a hierarchy that fills the gap between branching bisimulation and strong bisimulation.
As an example for its application we show how this definition gives rise to an advanced slicing procedure that creates a formula-specific slice, which constitutes a reduced model of the system that can be used as a substitute when verifying this formula. The result is a novel procedure for generating slices that are next-preserving branching bisimilar to the original model for any formula. We can assure that each slice preserves the formula it corresponds to, which renders the overall verification process sound.
68Q85 Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.)
68Q60 Specification and verification (program logics, model checking, etc.)
Full Text: DOI
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