Advances in asynchronous circuit theory. II: Bounded inertial delay models, MOS circuits, design techniques. (English) Zbl 0747.94024

Brzozowski, J. A.; Seger, C.-J. H.

Bull. EATCS 43, 199-263 (1991).

Summary: This is the second part of a survey of recent advances in the theory of asynchronous circuits; the first part appeared in the October 1990 issues of the EATCS Bulletin. In the first part, we dealt mostly with unbounded- delay models, and the theory was developed in terms of logic gates.
We consider the more realistic bounded-delay models, treating both the discrete and continuous cases. We then examine the complexity of asynchronous circuit analysis problems. After that, we briefly discuss mathematical models of MOS transistor circuits and extend the previously developed results to such circuits. Next, we turn our attention to the design of asynchronous circuits. Following, an overview of classical techniques, we include a short discussion of some modern design approaches, directing the reader to the literature for further details.

MSC:

94C10	Switching theory, application of Boolean algebra; Boolean functions (MSC2010)
68Q15	Complexity classes (hierarchies, relations among complexity classes, etc.)
94-02	Research exposition (monographs, survey articles) pertaining to information and communication theory

Keywords:

MOS switch-level models; design methodology; asynchronous circuits; logic gates; bounded-delay models; complexity of asynchronous circuit analysis