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Circuit synthesis with VHDL. (English) Zbl 0806.68004
The Kluwer International Series in Engineering and Computer Science 261. Dordrecht: Kluwer Academic Publishers (ISBN 0-7923-9429-1/hbk). xvi, 221 p. (1994).
Design methodologies and the standard design environment are discussed. It is essential reading for all students, researchers, design engineers and managers working with VHDL in a synthesis environment, an introduction to the use of VHDL logic (RTL) synthesis tools in design.
Chapter 1 is introductory. Chapter 2 – VHDL is studied in a more global way. Chapter 3 – all language constructs acceptable for synthesis purposes are systematically detailed. Chapter 4 – a complement to Chapter 3 – addresses the modelling-for-synthesis problem in a bottom-up approach. Chapter 5 discusses the necessary underlying methodology. Chapter 6 presents the synthesis standard environment. Chapter 7 – a real case of significant complexity is given in detail. In appendix the VHDL grammar summary (shorted, for synthesis) is given and the differences in VHDL’92 from VHDL’87 are underlined. The bibliography is given as notes on the bottom of pages. Index about 300 items.
Reviewer: H.Salum (Tallinn)
MSC:
68-01 Introductory exposition (textbooks, tutorial papers, etc.) pertaining to computer science
68Q45 Formal languages and automata
68N15 Theory of programming languages
94C10 Switching theory, application of Boolean algebra; Boolean functions (MSC2010)
94-01 Introductory exposition (textbooks, tutorial papers, etc.) pertaining to information and communication theory
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