An evolvable combinational unit for FPGAS. (English) Zbl 1100.94504

Sekanina, Lukáš; Friedl, Štěpán

Comput. Inform. 23, No. 5-6, 461-486 (2004).

Summary: A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e., as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e., to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and then used to design various circuits specified by randomly generated truth tables.

MSC:

94C10

Switching theory, application of Boolean algebra; Boolean functions (MSC2010)

Keywords:

combinational circuit; evolutionary design; evolvable hardware; field programmable gate array