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On formal equivalence verification of hardware. (English) Zbl 1142.68436
Hirsch, Edward A. (ed.) et al., Computer science – theory and applications. Third international computer science symposium in Russia, CSR 2008 Moscow, Russia, June 7–12, 2008. Proceedings. Berlin: Springer (ISBN 978-3-540-79708-1/pbk). Lecture Notes in Computer Science 5010, 11-12 (2008).
From the text: When modeling the logic functionality, hardware can be viewed as a Finite State Machine (FSM). The power-up state of hardware cannot be determined uniquely, therefore the FSM modeling the hardware does not have an initial state (or a set of initial states). Instead, it has a set of legal operation states, and it must be brought into this set of operation states from any power-up state by a reboot sequence.
For the entire collection see [Zbl 1136.68005].
MSC:
68Q60 Specification and verification (program logics, model checking, etc.)
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