zbMATH — the first resource for mathematics

Examples
Geometry Search for the term Geometry in any field. Queries are case-independent.
Funct* Wildcard queries are specified by * (e.g. functions, functorial, etc.). Otherwise the search is exact.
"Topological group" Phrases (multi-words) should be set in "straight quotation marks".
au: Bourbaki & ti: Algebra Search for author and title. The and-operator & is default and can be omitted.
Chebyshev | Tschebyscheff The or-operator | allows to search for Chebyshev or Tschebyscheff.
"Quasi* map*" py: 1989 The resulting documents have publication year 1989.
so: Eur* J* Mat* Soc* cc: 14 Search for publications in a particular source with a Mathematics Subject Classification code (cc) in 14.
"Partial diff* eq*" ! elliptic The not-operator ! eliminates all results containing the word elliptic.
dt: b & au: Hilbert The document type is set to books; alternatively: j for journal articles, a for book articles.
py: 2000-2015 cc: (94A | 11T) Number ranges are accepted. Terms can be grouped within (parentheses).
la: chinese Find documents in a given language. ISO 639-1 language codes can also be used.

Operators
a & b logic and
a | b logic or
!ab logic not
abc* right wildcard
"ab c" phrase
(ab c) parentheses
Fields
any anywhere an internal document identifier
au author, editor ai internal author identifier
ti title la language
so source ab review, abstract
py publication year rv reviewer
cc MSC code ut uncontrolled term
dt document type (j: journal article; b: book; a: book article)
An efficient VLSI linear array for DCT/IDCT using subband decomposition algorithm. (English) Zbl 1189.94025
Summary: Discrete Cosine transform (DCT) and inverse DCT (IDCT) have been widely used in many image processing systems and real-time computation of nonlinear time series. In this paper, a novel lineararray of DCT and IDCT is derived from the data flow of subband decompositions representing the factorized coefficient matrices in the matrix formulation of the recursive algorithm. For increasing the throughput as well as decreasing the hardware cost, the input and output data are reordered. The proposed 8-point DCT/IDCT processor with four multipliers, simple adders, and less registers and ROM storing the immediate results and coefficients, respectively, has been implemented on FPGA (field programmable gate array) and SoC (system on chip). The linear-array DCT/IDCT processor with the computation complexity $O(5N/8)$ and hardware complexity $O(5N/8)$ is fully pipelined and scalable for variable-length DCT/IDCT computations.

MSC:
94A08Image processing (compression, reconstruction, etc.)
WorldCat.org
Full Text: DOI EuDML
References:
[1] T.-Y. Sung, “Memory-efficient and high-performance 2-D DCT and IDCT processors based on CORDIC rotation,” WSEAS Transactions on Electronics, vol. 3, no. 12, pp. 565-574, 2006.
[2] M. Li and W. Zhao, “Representation of a stochastic traffic bound,” IEEE Transactions on Parallel and Distributed Systems, preprint. · doi:10.1109/TPDS.2009.162
[3] Ming Li, “Fractal time series-a tutorial review,” Mathematical Problems in Engineering, vol. 2010, Article ID 157264, 26 pages, 2010. · Zbl 1191.37002 · doi:10.1155/2010/157264 · eudml:224046
[4] M. Li and S. C. Lim, “Modeling network traffic using generalized Cauchy process,” Physica A, vol. 387, no. 11, pp. 2584-2594, 2008. · doi:10.1016/j.physa.2008.01.026
[5] C. Cattani, “Harmonic wavelet approximation of random, fractal and high frequency signals,” Telecommunication Systems, vol. 43, no. 3-4, pp. 207-217, 2010. · doi:10.1007/s11235-009-9208-3
[6] E. G. Bakhoum and C. Toma, “Mathematical transform of traveling-wave equations and phase aspects of quantum interaction,” Mathematical Problems in Engineering, vol. 2010, Article ID 695208, 15 pages, 2010. · Zbl 1191.35220 · doi:10.1155/2010/695208 · eudml:229128
[7] M. Li, “Generation of teletraffic of generalized Cauchy type,” Physica Scripta, vol. 81, no. 2, Article ID 025007, 2010. · Zbl 1191.90013 · doi:10.1088/0031-8949/81/02/025007
[8] M. Li and J.-Y. Li, “On the predictability of long-range dependent series,” Mathematical Problems in Engineering, vol. 2010, Article ID 397454, 9 pages, 2010. · Zbl 1191.62160 · doi:10.1155/2010/397454
[9] T. Y. Sung, “VLSI parallel and distributed computation algorithms for DCT processors,” in Proceedings of the IEEE International Phoenix Conference on Computer and Communications, pp. 121-125, Scottsdale, Ariz, USA, 1990.
[10] T. Y. Sung, “VLSI parallel and distributed processing algorithms for multidimensional discrete cosine transforms,” in Proceedings of the the Two-Track International Conference on Databases, Parallel Architectures, and Their Applications, pp. 36-39, Miami Beach, Fla, USA, March 1990.
[11] T. Y. Sung, “Novel parallel VLSI Architectures for discrete cosine transforms,” in Proceedings of the International Conference on Acoustics, Speech and Signal Processing, pp. 998-1001, Albuquerque, New Mexico, USA, April 1990.
[12] T. Y. Sung and Y. H. Sung, “A novel implementation of cost-effective parallel-pipelined 8\times 8 DCT processor,” in Proceedings of the 4th IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC ’04), pp. 200-203, Fukuoka, Japan, August 2004.
[13] T. Y. Sung, Y. S. Shieh, and H. C. Hsin, “Memory efficiency and high-speed architectures for forward and inverse DCT with multiplierless operation,” in Proceedings of the Advances in Image and Video technology, vol. 4319 of Lecture Notes in Computer Science, pp. 802-811, Springer, Berlin, Germany, December 2006.
[14] T. Y. Sung, Y. S. Shieh, and H. C. Hsin, “High-efficiency and low-power architectures for 2-D DCT and IDCT based on CORDIC rotation,” in Proceedings of the 7th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT ’06), pp. 191-196, December 2006.
[15] Y. H. Hu and Z. Wu, “An efficient CORDIC array structure for the implementation of discrete cosine transform,” IEEE Transactions on Signal Processing, vol. 43, no. 1, pp. 331-336, 1995. · doi:10.1109/78.365320
[16] H. Jeong, J. Kim, and W.-K. Cho, “Low-power multiplierless DCT architecture using image data correlation,” IEEE Transactions on Consumer Electronics, vol. 50, no. 1, pp. 262-267, 2004. · doi:10.1109/TCE.2004.1277872
[17] D. Gong, Y. He, and Z. Gao, “New cost-effective VLSI implementation of a 2-discrete cosine transform and its inverse,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 14, no. 4, pp. 405-415, 2004.
[18] V. Dimitrov, K. Wahid, and G. Jullien, “Multiplication-free 8\times 8 2D DCT architecture using algebraic integer encoding,” Electronics Letters, vol. 40, no. 20, pp. 1310-1311, 2004. · doi:10.1049/el:20046165
[19] M. Alam, W. Badawy, and G. Jullien, “A new time distributed DCT architecture for MPEG-4 hardware reference model,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 5, pp. 726-730, 2005. · doi:10.1109/TCSVT.2005.846429
[20] Y. P. Lee, T. H. Chen, L. G. Chen, and C. W. Ku, “A cost-effective architecture for 8\times 8 two-dimensional DCT/IDCT using direct method,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 7, no. 1, pp. 459-467, 1997.
[21] Y.-T. Chang and C.-L. Wang, “New systolic array implementation of the 2-D discrete cosine transform and its inverse,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, no. 2, pp. 150-157, 1995. · doi:10.1109/76.388063
[22] S.-F. Hsiao and W.-R. Shiue, “A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no. 11, pp. 1149-1159, 2001. · doi:10.1109/76.964780
[23] S.-F. Hsiao and J.-M. Tseng, “New matrix formulation for two-dimensional DCT/IDCT computation and its distributed-memory VLSI implementation,” IEE Proceedings. Vision, Image and Signal Processing, vol. 149, no. 2, pp. 97-107, 2002. · doi:10.1049/ip-vis:20020241
[24] H. S. Hou, “A fast recursive algorithm for computing the discrete cosine transform,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 10, no. 35, pp. 1455-1461, 1987.
[25] S.-F. Hsiao, W.-R. Shiue, and J.-M. Tseng, “Design and implementation of a novel linear-array DCT/IDCT processor with complexity of order Iog2 N,” IEE Proceedings. Vision, Image and Signal Processing, vol. 147, no. 5, pp. 400-408, 2000. · doi:10.1049/ip-vis:20000471
[26] Z. Cvetkovic and M. V. Popovic, “New fast recursive algorithms for the computation of discrete cosine and sine transforms,” IEEE Transactions on Signal Processing, vol. 40, no. 8, pp. 2083-2086, 1992. · Zbl 0758.65087 · doi:10.1109/78.150010
[27] E. Feig and S. Winograd, “Fast algorithms for the discrete cosine transform,” IEEE Transactions on Signal Processing, vol. 40, no. 9, pp. 2174-2193, 1992. · Zbl 0762.65103 · doi:10.1109/78.157218
[28] N. I. Cho and S. U. Lee, “Fast algorithm and implementation of 2-D discrete cosine transform,” IEEE transactions on circuits and systems, vol. 38, no. 3, pp. 297-305, 1991. · doi:10.1109/31.101322
[29] I. Koren, Computer Arithmetic Algorithm, chapter 5, A. K. Peters, Natick, Mass, USA, 2nd edition, 2005.
[30] T.-Y. Sung and H.-C. Hsin, “Design and simulation of reusable IP CORDIC core for special-purpose processors,” IET Computers and Digital Techniques, vol. 1, no. 5, pp. 581-589, 2007. · doi:10.1049/iet-cdt:20060075
[31] G. H. Golub and C. F. Van Loan, Matrix Computations, Johns Hopkins Studies in the Mathematical Sciences, chapter 6, Johns Hopkins University Press, Baltimore, Md, USA, 3rd edition, 1996.
[32] Xilinx FPGA products, http://www.xilinx.com/products/.
[33] “TSMC 0.18 CMOS Design Libraries and Technical Data, v.5.1,” Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, and National Chip Implementation Center (CIC), National Science Council, Hsinchu, Taiwan, 2009.
[34] Cadence design systems, http://www.cadence.com/products/pages/default.aspx.