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Data processing in the firmware systems for logic control based on search networks. (English. Russian original) Zbl 1365.93230
Autom. Remote Control 78, No. 1, 100-112 (2017); translation from Avtom. Telemekh. 2017, No. 1, 121-136 (2017).
Summary: It is proposed to use the hardware accelerators for analysis and data processing in the systems of logic control on a chip including the interacting processor system, memory, and configurable logic components. The data processing expected execution of operations over the sets of elements each of which can be activated by software and realized in the hardware in parallel networks admitting, if necessary, pipeline processing. New methods of design and use of the sorting and search networks are proposed, and the results of their theoretical and experimental comparison with existing networks are presented.
MSC:
93C30 Control/observation systems governed by functional relations other than differential equations (such as hybrid and switching systems)
93C83 Control/observation systems involving computers (process control, etc.)
94C99 Circuits, networks
Software:
Xilinx
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[1] Lee, E.A.; Seshia, S.A., Introduction to embedded systems: A cyber-physical systems approach, (2015)
[2] Jensen, J.C.; Lee, E.A.; Seshia, S.A., An introductory lab in embedded and cyber-physical systems, (2015)
[3] Rajkumar, R.; Lee, I.; Sha, L.; etal., Cyber-physical systems: the next computing revolution, 731-736, (2010)
[4] Vipin, K.; Shreejith, S.; Fahmy, S.A.; etal., Mapping time-critical safety-critical cyber physical systems to hybrid FPGAs, 31-36, (2014)
[5] Panunzio, M.; Vardanega, T., An architectural approach with separation of concerns to address extra-functional requirements in the development of embedded real-time software systems, J. Syst. Architect., 60, 770-781, (2014)
[6] Borangiu, A.; Popescu, D., Digital signal processing for knowledge based sonotubometry of Eustachian tube function, J. Control Eng. Appl. Inform., 16, 56-64, (2014)
[7] Sklyarov, V.; Skliarova, I., Digital Hamming weight and distance analysers for binary vectors and matrices, Int. J. Innovat. Comput., Inform. Control., 9, 4825-4849, (2013)
[8] Benmoussa, Y.; Boukhobza, J.; Senn, E.; etal., A methodology for performance/energy consumption characterization and modeling of video decoding on heterogeneous soc and its applications, J. Syst. Architect., 61, 49-70, (2015)
[9] Zmaranda, D.; Silaghi, H.; Gabor, G.; etal., Issues on applying knowledge-based techniques in real- time control systems, Int. J. Comput., Commun. Control, 8, 166-175, (2013)
[10] Sklyarov, V.A., Sintez avtomatov na matrichnykh BIS (Design of Automata on Matrix VLSI) Minsk: Nauka i Tekhnika, 1984.
[11] Sklyarov, V., Hierarchical finite-state machines and their use for digital control, IEEE Trans. VLSI Syst., 7, 222-228, (1999)
[12] Sklyarov, V., Reconfigurable models of finite state machines and their implementation in FPGAs, J. Syst. Architect., 47, 1043-1064, (2002)
[13] Baranov, S.I. and Sklyarov, V.A., Tsifrovye ustroistva na programmiruemykh BIS s matrichnoi strukturoi (Digital Devices on Programmable LSI), Moscow: Radio i Svyaz’, 1986.
[14] Sklyarov, V.; Skliarova, I., Hardware implementations of software programs based on HFSM models, Comput. Electr. Eng., 39, 2145-2160, (2013) · Zbl 1292.65038
[15] Santarini, M., Products, profits proliferate on zynq soc platforms, XCell, 88, 8-15, (2014)
[16] Santarini, M., Xilinx 16nm ultrascale+ devices yield 2-5X performance/watt advantage, XCell, 90, 8-15, (2015)
[17] Xilinx, Inc., Zynq-7000 All Programmable SoC Technical Reference Manual, 2014, http://www.xilinx.com/ support/documentation/user guides/ug585-Zynq-7000-TR M.pdf.
[18] Silva, J.; Sklyarov, V.; Skliarova, I., Comparison of on-chip communications in zynq-7000 all programmable systems-on-chip, IEEE Embedded Syst. Lett., 7, 31-34, (2015)
[19] Sklyarov, V.A., Microprocessor device for control of industrial equipment, Autom. Remote Control, 46, 102-105, (1985)
[20] Sklyarov, V., Skliarova, I., Silva, J., et al., Hardware/Software Co-design for Programmable Systems-on-Chip, Tallinn: TUT Press, 2014.
[21] Skliarova, I., Sklyarov, V., and Sudnitson, A., Design of FPGA-based Circuits Using Hierarchical Finite State Machines, Tallinn: TUT Press, 2012.
[22] Knuth, D.E., The Art of Computer Programming, vol. 3: Sorting and Searching, Reading: Addison-Wesley, 2011. · Zbl 0302.68010
[23] Pedroni, V., Compact Hamming-comparator-based rank order filter for digital VLSI and FPGA implementations, Proc. IEEE Int. Symp. on Circuits and Syst., 2, 585-588, (2004)
[24] Sklyarov, V.; Skliarova, I., Fast regular circuits for network-based parallel data processing, Adv. Electr. Comput. Eng., 13, 47-50, (2013)
[25] Teubner, J.; Mueller, R.; Alonso, G., Frequent item computation on a chip, IEEE Trans. Knowledge Data Eng., 23, 1-15, (2011)
[26] Sklyarov, V.; Skliarova, I.; Rjabov, A.; etal., Zynq-based system for extracting sorted subsets from large data sets, J. Microelectron., Electron. Components Mater., 45, 142-152, (2015)
[27] Sklyarov, V.; Skliarova, I., High-performance implementation of regular and easily scalable sorting networks on an FPGA, Microprocessors Microsyst., 38, 470-484, (2014)
[28] Mueller, R.; Teubner, J.; Alonso, G., Sorting networks on FPGAs, Int. J. Very Large Data Bases, 21, 1-23, (2012)
[29] Bunich, A.L.; Ginsberg, K.S.; Dobrovidov, A.V.; Zatuliveter, Yu.S.; Prangishvili, I.V.; Smolyaninov, V.V.; Sukhov, E.G., Parallel computation and control problems: A review, Autom. Remote Control, 63, 1867-1883, (2002) · Zbl 1116.93300
[30] Sklyarov, V., Skliarova, I., Barkalov, A., et al., Synthesis and Optimization of FPGA-based Systems, New York: Springer, 2014.
[31] Zakrevskij, A.; Sklyarov, V., The specification and design of parallel logical control devices, 1635-1641, (2000)
[32] Zakrevskii, A.D., Logicheskii sintez kaskadnykh skhem (Logical Design of the Cascade Circuits), Moscow: Nauka, 1981. · Zbl 0546.94021
[33] Sklyarov, V.; Skliarova, I.; Rjabov, A.; etal., Fast matrix covering in all programmable systems-on- chip, Electron. Electric. Eng., 20, 150-153, (2014)
[34] Kipfer, P. and Westermann, R., GPU Gems. Improved GPU Sorting, http://http.developer. nvidia.com/GPUGems2/gpugems2 chapter46.html.
[35] Batcher, K.E., Sorting networks and their applications, 307-314, (1968)
[36] Aj-Haj Baddar, S.W. and Batcher, K.E., Designing Sorting Networks. A New Paradigm, New York: Springer, 2011.
[37] Chamberlain, R.D.; Ganesan, N., Sorting on architecturally diverse computer systems, 39-46, (2009)
[38] Zuluada, M.; Milder, P.; Puschel, M., Computer generation of streaming sorting networks, 1245-1253, (2012)
[39] Sklyarov, V.; Skliarova, I., Design and implementation of counting networks, J. Comput., 97, 557-577, (2015) · Zbl 1336.68279
[40] Parhami, B., Efficient Hamming weight comparators for binary vectors based on accumulative and up/down parallel counters, IEEE Trans. Circuits Syst. II: Express Briefs., 56, 167-171, (2009)
[41] Sklyarov, V.; Skliarova, I.; Kabulov, A.V., Finding most frequently repeated data in the sorted arrays, Dokl. Uzbek Akad. Nauk, 4, 16-18, (2014)
[42] Sklyarov, V.; Skliarova, I.; Neves, A., Modeling and implementation of automatic system for garage control, 4295-4300, (2009)
[43] Sklyarov, V.; Skliarova, I., Modeling, design, and implementation of a priority buffer for embedded systems, 9-14, (2009)
[44] Digilent, Inc. ZyBo Reference Manual, http://digilentinc.com/Data/Products/ZYBO/ZYBO RM B V6. pdf. 2014.
[45] Avnet, Inc. ZedBoard (ZynqTM Evaluation and Development) Hardware User’s Guide, Version 2.2, http://www.zedboard.org/sites/default/files/, 2014.
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