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Pillai, R. V. K.; Al-Khalili, D.; Al-Khalili, A. J.; Shah, S. Y. A. A low power approach to floating point adder design for DSP application. (English) Zbl 0972.68005 J. VLSI Signal Process. Syst. Signal Image Video Technol. 27, No. 3, 195-213 (2001). MSC: 68M07 PDFBibTeX XMLCite \textit{R. V. K. Pillai} et al., J. VLSI Signal Process. Syst. Signal Image Video Technol. 27, No. 3, 195--213 (2001; Zbl 0972.68005) Full Text: DOI