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The Reduceron reconfigured and re-evaluated. (English) Zbl 1252.68066

Summary: A new version of a special-purpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.

MSC:

68N18 Functional programming and lambda calculus
68M20 Performance evaluation, queueing, and scheduling in the context of computer systems
68M99 Computer system organization

Software:

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References:

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