Vašíček, Zdeněk; Sekanina, Lukáš Hardware accelerator of cartesian genetic programming with multiple fitness units. (English) Zbl 1399.94121 Comput. Inform. 29, No. 6+, 1359-1371 (2010). Summary: A new accelerator of Cartesian genetic programming is presented in this paper. The accelerator is completely implemented in a single FPGA. The proposed architecture contains multiple instances of virtual reconfigurable circuit to evaluate several candidate solutions in parallel. An advanced memory organization was developed to achieve the maximum throughput of processing. The search algorithm is implemented using the on-chip PowerPC processor. In the benchmark problem (image filter evolution) the proposed platform provides a significant speedup (170) in comparison with a highly optimized software implementation. Moreover, the accelerator is 8 times faster than previous FPGA accelerators of image filter evolution. MSC: 94C30 Applications of design theory to circuits and networks 68P10 Searching and sorting Keywords:Cartesian genetic programming; hardware accelerator; evolutionary circuit design; FPGA PDFBibTeX XMLCite \textit{Z. Vašíček} and \textit{L. Sekanina}, Comput. Inform. 29, No. 6+, 1359--1371 (2010; Zbl 1399.94121)