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Co-synthesis of hardware and software for digital embedded systems. (English) Zbl 0846.68050

The Kluwer International Series in Engineering and Computer Science. 329. Dordrecht: Kluwer Academic Publishers. 266 p. (1995).
This is the revised edition of a dissertation submitted in 1993 to Stanford University. The book presents methodology for implementation of application-specific digital systems that contain both hardware and software components. Such synthesis approach is motivated by reasonable tradeoffs between costly but efficient purely hardware solution and much less expensive but often not enough efficient software on general-purpose system. The starting point for synthesis is high-level behavioral specification of the system and the set of performance constraints such as overall time (latency) to perform a given task, or more specifically on the timing to perform a subtask and/or on the ability to sustain specified input/output data rates over multiple executions of the system model. The exploration and systematic analysis of constraints is the key issue in decision how to partition the system into hardware and software.
The input for the synthesis procedure is an algorithmic description of system functionality described in hardware description language (HDL). A variety of HDL’s may be used (like VHDL or Verilog), although HardwareC language is preferred in the book. The HDL description is compiled into a graph, which allows to model the timing constraints and analyze them. Timing constraints are of two types – operation-delay and execution rate constraints. For the partition into hardware and software the cost model is formulated and partitioning feasibility is analyzed. Partitioning is based on iterative procedure – another approach would be difficult because of complicated nature of local and global properties of costs.
The primary objective of constraints analysis is to examine the mutual consistency of timing constraints and to answer the question about the existence of a system implementation that would satisfy the timing constraints. The analysis includes min/max delay and execution rate analysis – deterministic as well as probabilistic. The nexte step in overall system synthesis, that takes into account the results of constraints analysis is the software synthesis procedure. The software synthesis requires the linearization (serialization) in graph models and consists in three steps: generation of program threads, generation of program routines and code synthesis. The practical application of the co-synthesis framework is evidenced by two examples of synthesized ASIC’s – graphics and network controllers for general purpose computers. To conclude this book concerns relatively new, but important direction of research. The optimization of different peripheral controllers used in computers is of great importance, since it has great influence on the computing system efficiency. Another applications where ASIC designs should be optimized are industrial controllers. This book is valuable pace making contribution towards achieving maturity in synthesis systems.

MSC:

68W35 Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.)
68-02 Research exposition (monographs, survey articles) pertaining to computer science

Software:

Ptolemy
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